The present invention relates to a method and system for maintaining stress in an integrated circuit having field-effect transistor devices, and more specifically, to transforming an existing layout design of an integrated circuit into a modified layout design.
Semiconductor devices are used in a variety of electronic applications such as personal computers, cell phones, digital cameras and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
Multiple gate field-effect transistors (“MuGFET”) are a recent development in semiconductor technology which typically are metal oxide semiconductor field-effect transistors (“MOSFET”) that incorporate more than one gate into a single device. The multiple gates may be controlled by a single gate electrode, where the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. One type of MuGFET is referred to as fin-type field-effect transistor “FinFET,” which is a transistor structure with a fin-like semiconductor channel that is raised vertically out of the semiconductor surface of an integrated circuit.
In FinFETs, stress, e.g., uniaxial strain, in the fins contributes to the overall device performance. Strain relaxation occurs at locations near the ends of the fins when the fins are cut in manufactured integrated circuits having field-effect devices. In existing layout designs for manufactured integrated circuits having FinFETs, this strain relaxation of the fins degrades transistor performance due to mobility degradation.
Therefore, there is a need for improved design methods and systems for FinFETs which address the above disadvantages.